Generally speaking, computer systems include one or more central processor units (CPUs). Each CPU includes many signal paths that convey data between functional units that operate on that data. Such data is typically conveyed using a transfer cycle having a specified timing structure. That timing structure dictates a time period when the data to be transferred will be valid. Accordingly, the data is captured while it is valid and held for a specified amount of time. Such data capture can be performed using a number of level sensitive latches. Within a CPU, level sensitive latches are commonly implemented using a circuit that includes cross coupled inverters.
Logic circuits are often connected to the input or output terminals of level sensitive latches such that a logic function is performed on the logic levels developed thereby. For example, logic circuits are typically connected to the output terminals of level sensitive latches to implement set and reset functions.
One such logic circuit is a multiplexer circuit. The combination of a multiplexer and level sensitive latches is generally referred to as a multiplexer latch (mux-latch). A mux-latch senses the logic levels of data signals that are connected to its input terminals. A number of clock signals are connected to the mux-latch that indicate which of those input data signals is to have its logic level latched at the output thereof.
FIG. 1 illustrates a conventional mux-latch 100. The mux-latch 100 includes four inverters 102, 104, 106 and 108 and a keeper 110. The mux-latch 100 further includes two passgates 112 and 114 and an inverter 116 realized in CMOS technology. As those skilled in the art appreciate, an output of the inverter 116 is equal to Vcc when the p-device is “on” and the n-device is “off”.
The passgates 112 and 114 of the mux-latch 100 are each comprised of a p-device in parallel with an n-device. Therefore, the passgates 112 and 114 will be “on”, if an output from the inverters 102 and 106, respectively, is at a logic low level (0). The keeper 110 includes an inverter 118 and another inverter 120. The keeper 110 provides a weak output signal that maintains a signal output from the mux-latch. The keeper 110 maintains the output signal when clock signals CLKA and CLKB are at a logic low level (0). However, the keeper 110 is overridden when either of the passgates 112 or 114 is “on”.
The conventional keeper 110 illustrated in FIG. 1 is implemented with long channel devices. The use of these long channel devices increases the area and power consumption of the mux-latch 100. Furthermore, the use of the long channel devices decreases the speed of the mux-latch 100.